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[Software Engineering] spartan6_fpga_blockram_user_guide

Description: Spartan6　FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
Platform: | Size: 376832 | Author: james | Hits:

[VHDL-FPGA-Verilog] SLAVE_FIFO_16BITS

Description: 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
Platform: | Size: 1625088 | Author: xinsheng | Hits:

[Software Engineering] ThedesignofUniversalAsynchronousReceiverTransmitte

Description: 本课题所设计的UART支持标准的RS．232C传输协议，主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式，还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力，模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO，采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境，也能适合低速的数据传输场合，因此可以达到资源利用的最大化。-According to the characteristics of the UART and the portability advantage of FPGA designs，this paper puts forward an embedded UART design method based on FPGA chips．The design method includes description form of FSM and design approach of Top-Down．It’S good to take advantage of VHDL to program the slave module and top module of UART，and then integrate them into the interior of FPGA chip．In this case it improves not only the disadvantage of the traditional UART chips but also makes the whole system more compact and more reliable．
Platform: | Size: 5072896 | Author: mabeibei | Hits:

[Software Engineering] fifo

Description: 用FPGA完成256*8的存储器的读写操作- complete reading and writing 256* 8 memory with FPGA
Platform: | Size: 1024 | Author: 刘珊 | Hits:

[VHDL-FPGA-Verilog] memtest

Description: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar
Platform: | Size: 223232 | Author: 平凡 | Hits:

[VHDL-FPGA-Verilog] CoreSPI

Description: 数字电子设计fpga设计的spi接口的ip_core，可以直接用于在fpga设计，支持actel的fpga芯片，支持主从模式，fifo大小可选。-Fpga design of digital electronic design spi interface ip_core, fpga design can be directly used to support actel the fpga chip, support master-slave mode, fifo size options.
Platform: | Size: 1009664 | Author: zhangyujun | Hits:

[VHDL-FPGA-Verilog] sfifo

Description: verilog编写的同步FIFO，功能仿真完全正确，大家可以参考下。-verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
Platform: | Size: 1024 | Author: 查乐 | Hits:

[VHDL-FPGA-Verilog] uart_EP3C16_FIFO

Description: Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
Platform: | Size: 6756352 | Author: 515666524 | Hits:

[VHDL-FPGA-Verilog] CY7C68013FPGA

Description: USB控制芯片cy7c68013与FPGA通过slave fifo方式通信，块传输数据-USB controller chip and FPGA cy7c68013 way communication through the slave fifo, block data transfer
Platform: | Size: 961536 | Author: 张新 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于fpga的异步FIFO的设计和实现源代码-Fpga-based asynchronous FIFO design and implementation of source code
Platform: | Size: 3072 | Author: liyaning | Hits:

[VHDL-FPGA-Verilog] VGA-Controller

Description: FPGA do vga display controller. achieve include: fifo mem, vga core, rgb controller,
Platform: | Size: 7168 | Author: Aleks | Hits:

[VHDL-FPGA-Verilog] ad_da_ctr

Description: 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simulation results are basically correct.
Platform: | Size: 2299904 | Author: ych | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
Platform: | Size: 110592 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 基于FPGA的UART设计，包含接收模块，发送模块，FIFO模块-UART FPGA-based design, including the receiver module, sending module, FIFO module
Platform: | Size: 733184 | Author: 钱远盼 | Hits:

[VHDL-FPGA-Verilog] fifosy

Description: 用于对Xilinx FPGA FIFO的控制及读写-Xilinx FPGA FIFO
Platform: | Size: 1313792 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: sdram，在fpga数据传递领域应用广泛，乒乓操作，不同频域的数据传递，都靠sdram来转换。-SDRAM VHDL FPGA FIFO
Platform: | Size: 2058240 | Author: 梁 | Hits:

[VHDL-FPGA-Verilog] FPGA--VerilogFIFO

Description: FPGA串口通信程序 基于fifo读写的串口通信程序-FPGA serial communication program is based on the serial communication program to read and write fifo
Platform: | Size: 8192 | Author: 易浩 | Hits:

[VHDL-FPGA-Verilog] as_fifo1

Description: 实现异步FIFO功能，实现串行数据通讯功能，可以用FPGA实现串口扩展-Asynchronous FIFO functions, serial data communication
Platform: | Size: 1024 | Author: xzq | Hits:

[VHDL-FPGA-Verilog] fifo_vhdl

Description: 基于fpga,cpld的异步FIFO的设计 用VHDL语言进行相关的功能模块设计-Based on fpga, cpld design of asynchronous FIFO associated with VHDL design modules
Platform: | Size: 13312 | Author: 站长 | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:
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